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CAD Engineer- STA Methodology

Santa Clara Valley (Cupertino), California, United States


+ We are looking for candidates with:

+ 5+ years of relevant experience, including timing closure of gate level and transistor level designs in advanced CMOS process

+ A deep understanding of STA and methodologies for timing closure

+ A deep understanding of noise, cross-talk, and OCV effects

+ Excellent data analytical, problem solving, and interpersonal skills

+ Ability to work with multi-functional teams and drive decision-making

+ Prior experience delivering new designs to production under a very aggressive schedule

+ Additional requirements are knowledge of PrimeTime setup/flow automation, Spice simulation and understanding of derates and margins in typical STA/glitch noise closure

+ Programming experience in Perl, Python or Tcl is a requirement

+ Self-motivated and schedule oriented is a huge plus


In this exciting role, your responsibilities will include:

- Driving STA and noise methodology working with Design, CAD and Technology teams
- Working with the flow developers to incorporate timing closure requirements
- Documenting and helping with guidelines/specs
- Engaging parties in decision-making and working towards timely closure and thorough follow-through

**Education & Experience**

MS/BS in EE required

**Additional Requirements**

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* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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